1. Field of the Invention
The present invention generally relates to an abrasive and a polishing method, and in particular, relates to an abrasive and a polishing method that are used in a chemical mechanical polishing (CMP) process in a fabrication process for a semiconductor device.
2. Description of the Related Art
In a semiconductor device and a thin-film magnetic head, etc., a multi-layer structure provided by laminating films that are made be thinner by rolling has been employed. In particular, a multi-layer wiring structure has been employed in a semiconductor integrated circuit, in which wiring structures obtained by embedding a wiring pattern into an interlayer insulation layer formed on a substrate are laminated to be a multi-layer. In recent years, much more lamination and integration have been required with miniaturization of semiconductor integrated circuits.
Accordingly, when the multi-layer wiring structure is formed, a contact hole or a wiring slot is conventionally formed on the interlayer insulation layer and a metal layer is deposited on such an interlayer insulation layer so that the contact hole or the wiring slot is embedded. Then, such a metal layer is eliminated by means of polishing until the surface of the interlayer insulation layer is exposed, so that a flat wiring structure is formed. Since the upper principal surface of such a wiring structure is flat, a next wiring structure is easily formed thereon.
Speeding up as well as integration and miniaturization of semiconductor integrated circuits has been required. As the width of wiring is narrowed or the space of wiring is miniaturized for improving the integration, both wiring resistance (R) and wiring capacitance (C) are increased. Then, since the transmission time of a signal passing through the wiring is proportional to the product of R and C, RC delay occurs. While the length of the wire is shortened and the throughput speed of a semiconductor device is thus improved, the RC delay has become problematic in the total circuit delay of the semiconductor integrated circuit.
For improving the RC delay, the development of a dual damascene process using Cu (Cu dual damascene process) for a wiring material has been advanced in order to reduce the wiring resistance. In the dual damascene process, a slot for wiring and a contact hole for interlayer conduction are formed integrally in the interlayer insulation layer. The metal layer is deposited so that the slot and the contact hole are embedded with the wiring material. The metal layer is eliminated by means of polishing until the interlayer insulation layer is exposed, so that a flat wiring structure is formed. Additionally, in order to reduce the wiring capacitance, conventionally, SiO2 is used for the interlayer insulation layer and an organic thermosetting resin with a low-dielectric constant (low-k) has been examined.
In the polishing process, both the polishing and the elimination of the metal layer used for wiring, etc., are performed in a CMP (chemical mechanical polishing) method.
In Japanese Laid-Open Patent Application No. 2000-091284, the inventors of the present invention disclose that an abrasive including abrasive grains of MnO2 and an additive that contains NO3− has a selectivity such that W, Cu, and TiN, etc., as wiring materials can be polished with little polishing of SiO2 as the interlayer insulation layer in the semiconductor device. In such a polishing process, a process for adjusting the surface of a polishing cloth by using a dress jig is employed in order to improve the flatness of an object to be processed. In the dress jig, a fixed grindstone is used in which abrasive grains such as diamond, etc. are fixed with resin or epoxy. The inventors of the present invention found that the problem occurs that MnO2 as abrasive grains to polish the semiconductor device dissolves the resin or epoxy, and the abrasive grains of diamond, etc., detached from the fixed grindstone, are mixed with the abrasive on the surface of the polishing cloth, so as to damage the object to be processed.
The inventors also found that a problem occurs that since manganese oxides such as MnO, MnO2, Mn2O3 and Mn3O4 have oxidative effect, when an additive for eliminating oxides formed on the surface of an object to be processed is not contained in the abrasive, a metal or an intermetallic compound thereof as an object to be processed is oxidized during the polishing and an oxide layer is formed on the surface of the object to be processed, so that the object to be processed cannot be polished.
On the other hand, the materials used for the semiconductor device have been gradually diversified. For the wiring, W, Al, Cu, TiN, Ti, WN, Ta, TaN, etc., are used. Additionally, as a gate electrode, a metal or metal compound electrode could be realized from the requirement to lower the resistance of the electrode. In dual gate CMOS-type semiconductor devices, selected are different materials for gate electrodes suitable for P-channel MOS-type semiconductor devices and N-channel MOS-type semiconductor devices, respectively. FIG. 1 is a diagram showing examples of the materials for the gate electrodes. It is considered that a material having a work function close to a work function (an ideal value) suitable for the respective semiconductor device should be selected. Then, in the fabrication process, the gate electrode or wiring in which the above-mentioned metals are used is polished by a CMP method in the fabrication process of the semiconductor device. Accordingly, the problem occurs that abrasive grains suitable for the respective metals are used in the polishing process and various kinds of abrasive grain components are contained in the waste produced in the process, so that it becomes difficult to treat, recover and recycle the waste.
Additionally, in the polishing process, silica (SiO2), ceria (CeO2), alumina (Al2O3), zirconia (ZrO2), a manganese oxide, diamond, etc., mainstream in the CMP method at present, are employed as free abrasive grains and the amount of abrasive grains that contributes to the polishing effectively is equal to or less than 5% of feed. Also, since abrasive grains that do not contribute to the polishing are wasted without being recycled, the amount of the waste becomes too much and a problem from the viewpoint of effective use of resources occurs. However, from the viewpoint of efficient use of the abrasive grains, techniques for a fixed grindstone in which abrasive grains of manganese oxide are fixed with a binder are disclosed in Japanese Laid-Open Patent Application No. 11-207632, Japanese Laid-Open Patent Application No. 2000-6031, and Japanese Laid-Open Patent Application No. 2001-9731. Such a fixed grindstone has the effect that almost all the abrasive grains contribute to the polishing so as to reduce the amount of the waste. However, it is cumbersome and complicated to adjust the condition of the polishing because of a lack of uniformity in the abrasive grains embedded in the fixed grindstone, variation with time in regard to the ability of the polishing, and the dispersion of the polishing property among the individual fixed grindstones, etc. Thus, the production efficiency is lowered and polishing with a fixed grindstone has not yet become a technique to replace to polishing with free abrasive grains.
Furthermore, in Japanese Laid-Open Patent Application No. 9-22888, the inventors disclose that after polishing by using the abrasive grains of MnO2, the semiconductor device is washed by using an inorganic acid such as HCl, HNO3, H2SO4, HF, etc., and H2O2 so as to effectively eliminate MnO2 remaining in the semiconductor device. However, in a part of the washing condition, the problem occurs that wiring of Cu or Al embedded in the semiconductor device is corroded by the washing.